1. Field of the Invention
The invention relates to a test system and a method for testing a electric circuit.
In particular, the present invention relates to a test system for memory devices, in particular for DRAM units (DRAM=Dynamic Random Access Memory) using special test modes TM.
The present invention relates specifically to a test device for testing a circuit unit to be tested comprising a desired data stream generating device for providing a desired data stream that is fed to the circuit unit to be tested, a comparison device for comparing the desired data stream fed to the circuit unit to be tested, said desired data stream being fed to a reference terminal of the comparison device, with an actual data stream which is output from the circuit unit to be tested in a manner dependent on the desired data stream fed thereto and is fed to a test terminal of the comparison device, and the comparison device providing a corresponding comparison result, and an output unit for outputting the comparison result provided by means of the comparison device.
2. Description of the Prior Art
FIG. 3 shows a simplified block diagram of a conventional test device for testing a circuit unit DUT (Device Under Test) to be tested. In a manner dependent on a desired data stream (not shown) fed to the circuit unit DUT to be tested, an actual data stream ID is fed from the circuit unit DUT to be tested to a test terminal p of a comparison device VE. The comparison device furthermore receives a desired data stream SD via its reference terminal r.
The desired data stream SD is read out from a register R and adapted in a data scrambler S. The register has an input terminal E, via which a test data stream T can be fed to the register R and be stored therein. A comparison result v is obtained via an output terminal A, said comparison result enabling a statement as to whether the actual data stream fed to the test terminal p corresponds to the desired data stream SD that was fed to the reference terminal r of the comparison device VE.
In this case, it is necessary for the desired data stream SD and the actual data stream ID to be compared with one another bit by bit. A functionality of the circuit unit DUT to be tested is assumed only when the actual data stream ID completely matches the desired data stream SD.
The test costs when testing circuit units to be tested decrease as the number of circuit units that can be tested in a specific time increases, that is to say as the throughput rate increases. In order to reduce a test time and thus to save test costs, it is possible, then, either to decrease the test times or to increase the number of circuit units to be tested that can be tested in parallel per test system.
One specific test mode is the ACTM (Advanced Compression Test Mode), which enables particularly fast testing of the circuit units to be tested. In this case, the test data from which the desired data stream is obtained are stored in the register R, it being possible for the register R to be contained on the circuit unit DUT to be tested (not shown in FIG. 3). The data read out from the register R are then applied to an internal data bus and—if the circuit unit DUT to be tested is a memory device—written to the memory cells of the circuit unit DUT to be tested. When the corresponding memory information items are read out from the memory cells of the circuit unit to be tested, the data on the data bus are then compared with the desired data stream SD read out from the register R.
In order to check the functionality of the circuit unit DUT to be tested, it suffices for the comparison device VE to provide, as a comparison result v, an erroneous signal or an error-free signal (“pass”/“fail” result) at an output terminal A. Conventionally, an erroneous signal is represented by a logic “1” (high level) while an error-free signal is represented by a logic “0” (low level).
It is disadvantageous that with the conventional test device it is not possible to determine whether the comparison device can correctly identify all bit combinations that arise between the desired data stream SD and the actual data stream ID and are to be compared with one another. In an inexpedient manner, there is the possibility of a specific bit combination supplying an error-free signal (“pass” result) even though the data topology with regard to the desired data stream SD and the actual data stream ID were not identical.
In an unfavorable case, that is to say if an incorrect error-free signal (“pass” signal) is output to the output terminal A of the comparison device VE, a defective circuit unit to be tested would be regarded as error-free and be shipped.